1. Field of the Invention
The present invention relates to a method for fast programming nonvolatile memories, in particular flash memories, and to the relative memory architecture.
2. Description of the Related Art
As is known, in flash memories, reading, programming and erasing take place on different time scales: reading a word (formed by a preset number of bits, for example 8, 16, 32) often requires times shorter than 100 ns, programming a word requires times of about 10 μs, and erasing a sector (meaning thereby the group of memory cells that can be erased only simultaneously) lasts several hundreds of milliseconds (for example, 800 ms for a 512-kilobit sector).
Consequently, in a standard 32-Mb flash memory organized according to words, i.e., a memory wherein a word is the minimum unit on which it is possible to carry out reading and programming operations, programming of the entire memory array takes almost 20 sec., and erasure of all the sectors approximately 50 sec.
The last few years have witnessed a considerable market growth as regards many flash-memory applications; as a result, some customers require large quantities of these devices, even of the order of several million per year. Consequently, in-factory programming of such a large number of memories becomes ever more important for the customers, who thus demand flash memories that may be programmed in shorter times than current ones.
Standard programming of a single word currently takes place in three steps: sending a programming command; proper programming (during which the cells that make up the word to be programmed receive a high-voltage programming pulse); and verifying that programming has been successful.
Proper programming is the most burdensome in terms of time, in so far as the other steps (respectively represented by a cycle operation on the pins and a reading operation) may last less than 1 μs.
Proper programming requires the generation of high voltages. This may take place either internally (single-supply flash memories) or externally (double-supply flash memories). In the second case, which will be considered hereinafter, the memory is able to generate the programming voltage in very short times starting from a voltage supplied from outside and far higher than standard voltage supply (up to 12 V). In addition, the memory is able to parallel program all the cells that store each word (hereinafter also referred to collectively as a memory location). In this case, moreover, the memory is also able to carry out parallel programming of more than one word, even though the latter mode would entail considerably high circuit complication (and hence large overall dimensions), since the memory should include special registers for addresses and patterns of the words to be stored (meaning by patterns of the words the sequences of bits of each word).
In order to reduce the programming time, various programming modes have been developed.
For example, certain memories enable abbreviated modes of command writing (commonly referred to as “Unlock Bypass Mode”).
In addition, flash memories are available on the market that are provided with a programming mode, referred to as “Factory Program”, purposely designed for mass production, where for each memory device even millions of memory locations have to be programmed in the factory.
According to this programming mode, the memory locations are written in sequence in successive addresses using a double supply voltage. For this purpose, first blind programming pulses are sent to the locations to be written and, at the end of the blind writing, sequential verification is carried out on all the locations written. During verify, the user must repeat, for each address, the programmed pattern of each location and, only if verify of a individual location fails, a standard programming of the location is carried out.
In detail, according to the “factory program” mode, the user initially supplies a command for activating the programming step; issues a command for executing a chip-enable (CE#) cycle which defines the initial address and the pattern that is to be programmed at this address; the pattern is written in the memory, and execution of the operation is confirmed by a “ready” signal; upon reception of the “ready” signal, the user carries out a subsequent CE# cycle, providing the new pattern to be programmed in the next position. In order to terminate the blind-programming step, the user must supply the address of a sector different from the initial one; this sending is then interpreted by the memory as end of programming and start of the verify step. In other words, once the initial address has been defined, by means of a successive CE# cycle the user supplies, to the memory, patterns that are written in subsequent addresses. The address increment thus takes place within the memory.
Verify follows the same logic.
In this way, the internal voltages necessary for programming and verifying are generated only once for the entire sequence of words to be programmed and verified, instead of for each word to be written.
An important advantage of the “factory program” mode lies in the fact that the type of interface used, wherein the address of the locations to be programmed is calculated within the memory and does not have be supplied by the programmer, is particularly suited to the majority of the programming devices currently available on the market, thus enabling the time of handshake between the user and the memory to be considerably reduced.
Consequently, the “factory program” mode is undoubtedly so far the one affording the best performance in flash memories. Standard programming requires in fact 8 μs/word; with the Unlock Bypass mode and double supply voltage the time reaches 5 μs/word, and with the “factory program” mode it drops to as few as 3.5 μs/word.
Nevertheless, the market demands ever faster memories, and consequently the problem arises of how to reduce the programming times further.